Experiment to perform logic of JK FLIP FLOP on kit

J

K

CLK













      TRUTH TABLE                               

Serial No. clock J K Q(n-1) Q̅(n-1) Q Remark

      CLOCK DIAGRAM                                               

Vcc: +5V

R1: 330ohm

LED 1

R2: 330ohm

LED 2

Q

CLK=0

CLK=1

J=0

J=1

K=0

K=1

Q=0

Q=1

Q̅=0

Q̅=1

SUPPLY

GND